Semiconductor processing includes many patterning steps, wherein a device design is first transferred to a lithographic mask and the mask is exposed to a light source, resulting in the printing of the pattern on a photoresist film deposited on a layer stack that is built up layer by layer on a semiconductor wafer. After development of the resist, etching transfers the pattern to a layer of the stack, for example for realizing a metal conductor pattern in a level of the back-end-of-line stack of an integrated circuit chip. Subsequent processing may also include additional deposition, etch and polish steps to further modify the pattern, such as in self-aligned multiple patterning. Feature dimensions of the patterns in present day processing technology are of the order of nanometers, and the monitoring of the features includes specific metrology tools. The main dimension of interest is referred to as the critical dimension (CD) of rectilinear features of physical patterns at each of the various processing steps.
Current methods for measuring CD variation have significant drawbacks: (a) High resolution methods such as Scanning Electron Microscopy (SEM) or Atomic Force Microscopy (AFM) are relatively slow, expensive, and potentially destructive (particularly to resist patterns). Current optical methods (e.g., scatterometry) include model development for each pattern and process configuration, are difficult to calibrate and susceptible to variation in underlying film stacks. There may be a need therefore for alternative methods that allow a reliable and non-intrusive way of verifying the critical dimensions of printed and/or etched pattern features.
Self-aligned multi-patterning SAxP is a method essential to semiconductor density scaling. It is a technique of multiplying, typically doubling (SADP) or quadrupling (SAQP), the spatial periodicity of regular arrays by the formation of sidewall spacers on a periodic mandrel (aka, core) structure. To achieve uniform periodicity in the final array, the width dimension of the mandrel elements might be controlled relative to their pitch and to the spacer width. In the SAQP example, the mandrel pitch may be 128 nm, the width of the spacer 16 nm, so that the mandrel element width might be controlled at 48 nm to result in an SAQP pitch of 32 nm. A variation of the mandrel width results in a variation of the nominal 32 nm pitch across the array, known as “pitch walking.” Pitch walking is a significant failure mechanism in semiconductor manufacturing. Current methods of pitch walking metrology and control are slow, expensive and error-prone.